About this role
Tenstorrent seeks a contractor to own full-custom analog/mixed-signal IC layout for advanced FinFET nodes. You'll translate schematics into manufacturable layouts for high-performance IP blocks and integrate them into complex SoCs. Remote role based in North America with compensation ranging $100K-$500K.
Must have
5 years experience in analog/mixed-signal IC layout with silicon in CMOS/FinFET nodes
Deep proficiency in Cadence Virtuoso XL/GXL or equivalent custom layout environments
Strong understanding of CMOS devices, interconnect stacks, and advanced-node rules
Fluency in physical verification flows for DRC, LVS, ERC, LPE/RC, DFM, and antenna checks
Experience designing for matching, coupling/noise, IR/EM, ESD, and latch-up
Ability to own complex blocks independently and communicate with distributed teams
Technologies
Responsibilities
Partner with circuit designers to implement full-custom analog/mixed-signal layouts for PLLs, VCOs, ADCs, DACs, LDOs, and high-speed I/O
Build optimized floorplans and routing balancing area, parasitics, matching, and congestion
Apply best-practice layout techniques including common-centroid devices, symmetric routing, guard rings, and shielding
Run and debug DRC, LVS, ERC, DFM, and antenna checks driving all violations to closure
Support post-layout extraction and simulation iterating with circuit designers for spec closure
Develop layout methodology and automation in Python, Tcl, and SKILL to raise team productivity
Benefits
Recruitment process
Role is remote based out of North America
Candidates assessed for appropriate level during interview process
Compensation ranges from $100K-$500K including base and variable targets
Offer contingent upon eligibility to access U.S. export-controlled technology
U.S. export law restrictions apply based on citizenship or residency status
Company develops high-performance RISC-V CPUs and AI platforms
Equal opportunity employer
